The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC manufacturing are needed. For example, as semiconductor devices, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), are scaled down through various technology nodes, strained source/drain features (e.g., stressor regions) have been implemented using epitaxial (epi) semiconductor materials to enhance carrier mobility and improve device performance. Forming a MOSFET with stressor regions often includes using epitaxially grown silicon (Si) to form raised source and drain features for an n-type device, and epitaxially growing silicon germanium (SiGe) to form raised source and drain features for a p-type device. However, approaches known to the Applicants have not been entirely satisfactory in all respects.